The present invention relates to a semiconductor integrated circuit including a CMOS gate array.
Hitherto, in large scale integrated (LSI) circuits, gate array chips constituted in such a manner that transistors or cells are arranged over substantially the entire surface of a master chip without preliminary allotment of a specified region for wiring, have been known. In such a gate array chip, the area ratio between the wiring region and the cell region can almost be arbitrarily selected in the circuit connection step. Therefore, in such a gate array chip the area ratio between the wiring region and the cell region can be properly set in accordance with the kinds of circuit systems to be formed. Namely, in the case of a circuit system having a small number of or a small area for the wirings in contrast to the number of cells, a large cell region is set. In contrast, in the case of a circuit system having a large number of wirings or a large area for the wirings in contrast to the number of cells, a small cell region is set. Therefore, the whole gate array chip can be efficiently used.
In partial gate-type gate array chips in which the wiring region is preliminarily allotted independent of the cell region, transistors or cells are formed in the preliminarily defined cell region, so that a RAM, a ROM, a PLA, or the like cannot be formed with a high degree of density. However, in full gate-type gate array chips in which cells are formed over the whole surface, the wiring region which requires a large area is not preliminarily allotted. Instead, this wiring region is selectively allotted in accordance with the circuit to be formed, the advantage being that a circuit such as a RAM, a ROM, or a PLA, etc. can be formed with high density. Therefore, it is necessary to design the structure of the cell carefully in order to make full use of this advantage.
The following conditions are required to make the best of the advantage of the full gate-type gate array chip.
(1) Transistors or cells must be formed with a high degree of density.
(2) In full gate-type gate array chips, the stray capacitance existing between the metal wiring and the substrate or transistor formed under this metal wiring is larger than that in partial-gate type gate array chips. Therefore, to improve the operating speed, a transistor having a large load driving capability needs to be formed.
(3) Although the width of the wiring region is variable, it is constituted step by step and therefore the width of this wiring region must be finely altered.
FIGS. 1 to 3 show parts of patterns of conventional full gate-type gate array chips having a plurality of basic cell arrays arranged like a matrix. However, the basic cell arrays used in these chips do not sufficiently satisfy the above-mentioned three conditions.
In the gate array chip pattern shown in FIG. 1, the basic cell array surrounded by the broken line includes a pair of p-channel MOS transistors TP1 and TP2, and a pair of n-channel MOS transistors TN1 and TN2. The p-channel MOS transistors TP1 and TP2 have p.sup.+ -type impurity regions 1 to 3 formed in an n-type substrate and serving as source and drain regions, as well as gate electrodes G1 and G2 arranged in parallel with each other. The impurity region 2 is used as a drain region of one of the MOS transistors TP1 and TP2, and is simultaneously used as a source region of the other of the MOS transistors TP1 and TP2. The n-channel MOS transistors TN1 and TN2 have n.sup.+ -type impurity regions 4 to 6 formed in a p-type substrate and serving as source and drain regions, and gate electrodes G3 and G4 arranged in parallel with each other. The impurity region 4 is used as a drain region of one of the MOS transistors TN1 and TN2 and is simultaneously used as a source region of the other of the MOS transistors TN1 and TN2.
The gate electrodes G1 and G2 where is the other hand are arranged on the same line as the gate electrodes G3 and G4, respectively. As described above, in this gate array chip, MOS transistors of the same type are formed on the same column, while p- and n-channel MOS transistors are alternately arranged on the same row. In the diagrams, a plurality of dots arranged in a matrix are drawn to express the dimensions of each element. The distance between two adjacent dots is one grid, or about 5 .mu.m.
Generally, in integrated circuits, the reference potential region is formed in each substrate region to maintain the substrate potential at a reference potential level. In FIG. 1, these reference potential regions are shown as diffusion regions 7-1 and 7-2, which are formed to have the same conductivity type as the substrate regions, that is, n- and p-type conductivity types, and to extend in the column direction closest to the basic cell arrays on the same column. In order to provide spaces for the diffusion regions 7-1 and 7-2, it is required to separate the adjacent basic logic cell arrays from each other by about two grids in the row direction.
FIG. 2 shows the pattern of a gate array chip which is substantially the same as that shown in FIG. 1, except that two diffusion regions 8-1 and 8-2, forming the reference potential regions, are arranged on a line in the row direction in each basic cell array. In the basic cell array of the gate array chip shown in FIG. 2, as compared with that shown in FIG. 1, the dimension in the row direction can be reduced by one grid, while the dimension in the column direction is enlarged by one grid.
FIG. 3 shows the pattern of a gate array chip in which two diffusion regions 9-1 and 9-2 forming the reference potential regions are arranged between the gate electrodes G1 and G2, and between the gate electrodes G3 and G4 in each basic cell array. In this basic cell array of the gate array chip, separation of the diffusion regions 9-1 and 9-2 from the drain or source region of the MOS transistor is necessary. Therefore, in order to provide the space to form the diffusion regions 9-1 and 9-2, it is necessary to elongate the gate electrode of each MOS transistor by one grid in the row direction, as compared with that shown in FIGS. 1 or 2.
As described above, in the gate array chips shown in FIGS. 1 to 3, in order to provide the spaces to form the diffusion regions 7-1, 7-2 to 9-1, 9-2, the dimension in the row or column direction of each basic cell array is enlarged.